Programmably configurable digital filter

ABSTRACT

A digital filter includes a plurality of connected component digital filters. Control signal generation circuitry is configured to receive a tap output signal from each of at least some of the component digital filters and to process the received tap output signals to generate a control signal to output from the control signal circuitry. Output processing circuitry is configured to process an output of one of the plurality of component digital filters, based on the control signal generated by the control signal circuitry, to generate an output of the digital filter. The processing of the received tap output signals by the control signal generation circuitry may be, for example, programmably configurable.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. 119(e) from ProvisionalU.S. Patent Application Ser. No. 60/620,229, filed Oct. 18, 2004 (Atty.Docket No. GENSP094P), entitled “PROGRAMMABLE WIDE BAND FILTER”, whichis incorporated herein by reference in its entirety.

BACKGROUND OF INVENTION

1. Technical Field

The present invention is in the field of digital filters and, inparticular, relates to digital filters that are programmablyconfigurable.

2. Background

A typical method to adjust the response of a digital filter includeschanging the filter tap configuration and changing the coefficients ofthe component digital filters. It is desirable to have the ability toprovide greater flexibility while, for example, employing standarddigital filter components in a standard configuration.

SUMMARY OF THE INVENTION

A digital filter includes a plurality of component digital filtersconnected in a particular configuration. Control signal generationcircuitry is configured to receive a tap output signal from each of atleast some of the component digital filters and to process the receivedtap output signals to generate a control signal to output from thecontrol signal circuitry. Output processing circuitry is configured toprocess an output of one of the plurality of component digital filters,based on the control signal generated by the control signal circuitry,to generate an output of the digital filter. The processing of thereceived tap output signals by the control signal generation circuitrymay be, for example, programmably configurable.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 broadly illustrates a programmable digital filter circuit inaccordance with one example, where the component digital filters areconnected in a pure serial manner.

FIG. 2 illustrates an example of the control signal generation circuitryof the FIG. 1 circuit.

FIG. 3 illustrates an example programmable digital filter where thecontrol signal generation circuit employs a logical comparison.

FIG. 4 illustrates an example programmable digital filter where thecontrol signal generation circuit employs a divider.

FIG. 5 illustrates a particular example of the FIG. 3 exampleprogrammable digital filter circuit.

FIG. 6 illustrates a particular example of the FIG. 4 exampleprogrammable digital filter circuit.

FIG. 7 illustrates an example frequency response of the BPF1 digitalfilter of the FIG. 5 and FIG. 6 circuits.

FIG. 8 illustrates an example frequency response of the BPF2 digitalfilter of the FIG. 5 and FIG. 6 circuit.

FIG. 9 illustrates the overlap of the FIG. 7 example frequency responseof the BPF1 digital filter and the FIG. 8 example frequency response ofthe BPF2 digital filter.

FIG. 10 illustrates the combined frequency response of the BPF1 digitalfilter and the BPF2 digital filter, based on the configuration of thecontrol signal generation circuitry using the programmable LIMITparameter, including both a maximum frequency response (LIMIT=0) and aminimum frequency response (LIMIT=15).

FIG. 11 illustrates another example programmable digital filter circuitwhere the component digital filters are connected in parallel.

DETAILED DESCRIPTION

FIG. 1 illustrates an example digital filter 100 in accordance with abroad aspect. The digital filter 100 is a fixed tap based filter with adynamically operational logical block. In particular, the digital filter100 includes a first component digital filter 102 and a second componentdigital filter 104, connected in a particular configuration. In the FIG.1 example, the component digital filters are connected serially. In someexamples, additional digital filters may be connected in theconfiguration, serially or in parallel, or a combination of both.

Output processing circuitry 106 processes the output of the digitalfilter 104, based on a control signal, to provide an output of thedigital filter 100. The control signal is generated by control signalgeneration circuitry 108, which is a dynamically operational logicblock. The control signal is generated based on a tap output signal 103provided from the output of digital filter 102 and a tap output signal105 provided from the output of the digital filter 104.

FIG. 2 broadly illustrates one example of the control signal generationcircuitry 108. First component control signal generation circuit 202 agenerates a component control signal 203 a based on the tap outputsignal 103. Second component control signal generation circuit 202 bgenerates a component control signal 203 b based on the tap outputsignal 105. Combiner circuitry 204 combines the component control signal203 a and the component control signal 203 b to generate the controlsignal to output from the control signal generation circuitry 108. Asdiscussed above relative to FIG. 1, the output processing circuitry 106processes the output of the digital filter 104 based on the controlsignal output from the control signal generation circuitry 108.

In some examples, one, some or all of the component control signalgeneration circuitry 202 a, component control signal generationcircuitry 202 b and the combiner circuitry 204 are programmablyconfigurable. FIG. 2 illustrates programmable input signals 206 providedto the control signal generation circuitry 108. In particular, FIG. 2illustrates programmable input signal 206 a provided to componentcontrol signal generation circuitry 202 a, programmable input signal 206b provided to component control signal generation circuitry 202 b, andprogrammable input signal 206 c provided to combiner circuitry 204. Someexamples of the particular programmable configurability are discussedrelative to later figures. The programmable input signals 206 may beprovided by, for example, a programmable processor such as amicroprocessor or other programmable circuitry, such as one or moreApplication Specific Integrated Circuits.

FIG. 3 illustrates a digital filter 300 in which the processing in thecontrol signal generation circuitry 108 (denoted in FIG. 3 by referencenumeral 302) may include, for example, logical comparison of signalsbased on the tap output signal 103 and on the tap output signal 105. Theprocessing by the output processing circuitry 106 (denoted in FIG. 3 byreference numeral 304) may include, for example, gain/attenuationprocessing.

FIG. 4 illustrates a digital filter 400 in which the processing in thecontrol signal generation circuitry 108 (denoted in FIG. 4 by referencenumeral 402) may include, for example, determining a ratio betweensignals based on the tap output signal 103 and on the tap output signal105.

FIG. 5 illustrates a particular example 500 of the FIG. 3 digital filter300, in which a particular example of the generalized control signalgeneration circuitry 302 of FIG. 3 is shown as control signal generationcircuitry 502. In particular, averaging circuitry 504 a and averagingcircuitry 504 b are coupled to receive the tap output signal 105 and thetap output signal 103, respectively. The output of averaging circuitry504 a is a control signal representing the frequency response of tapoutput signal 105, and the output of averaging circuitry 504 b is acontrol signal representing the frequency response of tap output signal103. In one example, the window size of the averaging circuitry 504 aand/or the averaging circuitry 504 b is programmable to, for example,two, four or eight samples. This programming could be accomplished usingthe programmable input signal 206 b and the programmable input signal206 a, respectively, as shown in FIG. 2.

Since the tap output signal 105 is from the digital filter whichreceives as input the tap output signal 103, the tap output signal 105has a combined frequency response of the digital filter 102 and thedigital filter 104; and the output of averaging circuitry 504 a is acontrol signal representing the combined frequency response of thedigital filter 102 and the digital filter 104.

Differencing circuitry 506 determines a difference between the controlsignal output from averaging circuitry 504 b and from averagingcircuitry 504 a, and the output of the differencing circuitry 506 isprovided to clip circuitry 508. Clip circuitry 508 clips the output ofthe differencing circuitry 506 to zero as appropriate.

Limiting circuitry 510 receives the output of clip circuitry 508 andlimits the output based on a limiting factor LIMIT (which may also beprogrammable, in a manner similar to the programmable input signal 206 aand the programmable input signal 206 b). In one example, the limitingcircuitry 51 carries out the following operations:

-   if the output of the clip circuitry 508 is less than LIMIT, then the    limiting circuitry 510 divides the output of the clip circuitry 508    by LIMIT and provides the result at the output of the limiting    circuitry 510;-   and if the output of the clip circuitry 508 is greater than or equal    to LIMIT, then the limiting circuitry sets the output of the    limiting circuitry 510 to one.

The output of the limiting circuitry 510 is then employed by thegain/attenuating circuitry 304 as a control signal to controlgain/attenuation processing. In one example, the output of thegain/attenuation circuitry 304 is the signal at the tap 105 multipliedby a factor of one minus the output of the limiting circuitry 510. Forexample, the limiting factor LIMIT may be a four-bit value programmablefrom a minimum of zero (0000b) up to a maximum of 15 (1111b). With thelimiting factor LIMIT at 15, the attenuation factor will be a maximum of0.0625, so if the averaged sample difference is greater than 15, theoutput of the digital filter 500 will be completely attenuated. Byprogramming the limiting factor LIMIT from 0 to 15, there can bedifferent response curves, changing the roll-off response of the digitalfilter 500. As a result, the passband response is maintained, while therolloff/cutoff response is programmable (for example to achieve asharper response).

FIG. 6 illustrates a particular example 600 of the FIG. 4 digital filter400, in which a particular example of the generalized control signalgeneration circuitry 402 of FIG. 4 is shown as control signal generationcircuitry 602. The Figure example 600 may be considered similar in mostrespects to the FIG. 5 example. However, the outputs of the averagingcircuitry 504 a and 504 b are not differenced. Rather, a ratio of theoutputs is determined. The clip/limiting circuitry 608/610 clips theresult to be between zero and LIMIT (the programmable limiting factor).The resulting control signal is then employed by the gain/attenuatingcircuitry 304 as a control signal to control gain/attenuationprocessing.

It is instructive to inspect the example frequency response graphsillustrated in FIG. 7, FIG. 8, FIG. 9 and FIG. 10. FIG. 7 illustrates anexample frequency response of the of BPF1 102; FIG. 8 illustrates anexample frequency response of the BPF2 104; and FIG. 9 illustrates thefrequency responses of FIG. 7 and FIG. 8 on a single graph for easiercomparison. FIG. 10 illustrates an example output-controlled combinedfrequency response of, for example, the example 500 (FIG. 5) or theexample 600 (FIG. 6). In FIG. 10, the response 1002 represents a maximumbandwidth response of the circuitry (i.e., using the particular examplesdiscussed above, with LIMIT programmed to zero) whereas the response1004 represents a minimum bandwidth response of the circuitry (i.e.,again using the particular examples discussed above, with LIMITprogrammed to fifteen).

By making the attenuation factor programmable (i.e., by having thelimiting factor LIMIT be programmable), and referring specifically toFIG. 10, different bandwidth responses can be achieved between andincluding the minimum response 1002 and the minimum response 1004.

FIG. 11 illustrates an example 1100 where the component digital filters102 and 104 are connected in parallel. The outputs of the componentdigital filters are provided to the control signal generation circuitry108, which controls the output processing by the output processingcircuitry 106. In yet other examples, a plurality of component digitalfilters are connected in a combination of serially and in parallel.

In general, by making the control signal generation circuitry 108programmable based on tap outputs of the component digital filters, thecharacteristics of digital filter can be modified without makingstructural changes such as changing filter coefficients and changing thefilter tap output configuration. Minimization of ringing and sharperresponse can be achieved, and properties of the digital filter 100 canbe controlled adaptively for various applications.

1. A digital filter, comprising: a plurality of connected componentdigital filters; control signal generation circuitry configured to:receive a tap output signal from each of at least some of the componentdigital filters; and process the received tap output signals to generatea control signal to output from the control signal circuitry; and outputprocessing circuitry configured to process an output of one of thecomponent digital filters, based on the control signal generated by thecontrol signal circuitry, to generate an output of the digital filter.2. The digital filter of claim 1, wherein: processing the received tapoutput signals by the control signal generation circuitry isprogrammably configurable.
 3. The digital filter of claim 2, wherein:processing the received tap output signals by the control signalgeneration circuitry includes a plurality of independently programmablyconfigurable portions.
 4. The digital filter of claim 3, wherein: eachof at least some of the independently programmably configurable portionsindependently process a separate one of the received tap signals.
 5. Thedigital filter of claim 4, wherein: others of at least some of theindependent programmably configurable portions do not independentlyprocess a separate one of the received tap signals.
 6. The digitalfilter of claim 4, wherein: the portions that each independently processa separate one of the received tap signals perform averaging of theseparate one of the received tap signals.
 7. The digital filter of claim1, wherein: the control signal generation circuitry is configured toreceive at least one input parameter signal; and the step of processingthe received tap outputs includes processing the received tap outputsbased on the at least one input parameter signal.
 8. The digital filterof claim 7, further comprising: circuitry including a programmableprocessor, configured to determine the at least one input parametersignal and to provide the at least one input parameter signal to thecontrol signal circuitry.
 9. The digital filter of claim 1, wherein: thecontrol signal generation circuitry includes a plurality of componentcontrol signal generation circuitry, each component control signalgeneration circuitry configured to generate a separate component controlsignal based on a separate one of the tap outputs; and control signalcombining circuitry configured to process the separate component controlsignals, to generate the control signal to output from the controlsignal generation circuitry.
 10. The digital filter of claim 9, wherein:the control signal combining circuitry is configured to process theseparate component control signals by at least performing a logicalcomparison of the separate component control signals.
 11. The digitalfilter of claim 10, wherein: performing the logical comparison includesperforming an arithmetic difference on the separate component controlsignals.
 12. The digital filter of claim 10, wherein the control signalcombining circuitry is configured to process the separate componentcontrol signals by, further, performing limit processing on a result ofthe logical comparison of the separate component control signals. 13.The digital filter of claim 12, wherein the performing of limitprocessing is programmably configurable.
 14. The digital filter of claim11, wherein the control signal combining circuitry is configured toprocess the separate component control signals by, further, performinglimit processing on a result of the arithmetic difference of theseparate component control signals.
 15. The digital filter of claim 14,wherein the performing of limit processing is programmably configurable.16. The digital filter of claim 9, wherein: the control signal combiningcircuitry is configured to process the separate component controlsignals by at least performing a ratio of the separate component controlsignals.
 17. The digital filter of claim 14, wherein: performing theratio includes performing an arithmetic division on the separatecomponent control signals.
 18. The digital filter of claim 16, whereinthe control signal combining circuitry is configured to process theseparate component control signals by, further, performing limitprocessing on a result of the ratio of the separate component controlsignals.
 19. The digital filter of claim 18, wherein the performing oflimit processing is programmably configurable.
 20. The digital filter ofclaim 17, wherein the control signal combining circuitry is configuredto process the separate component control signals by, further,performing limit processing on a result of the arithmetic difference ofthe separate component control signals.
 21. The digital filter of claim20, wherein the limit processing is programmably configurable.
 22. Thedigital filter of claim 20, further comprising: circuitry including aprogrammable processor, configured to programmably configure eachcomponent control signal generation circuitry and the control signalcombining circuitry.
 23. The digital filter of claim 9, wherein: eachcomponent control signal generation circuitry performs an average of theassociated separate one of the tap outputs.
 24. The digital filter ofclaim 23, wherein: each component control signal generation circuitry isindependently programmably configurable.
 25. The digital filter of claim24, wherein: an averaging window of each component control signalgeneration circuitry is independently programmably configurable.
 26. Thedigital filter of claim 9, wherein: the control signal combiningcircuitry performs clip processing on a combination of the separatecomponent control signals.
 27. The digital filter of claim 26, wherein:the clip processing of the control signal combining circuitry isindependently programmably configurable.
 28. The digital filter of claim27, wherein: a clip limit of the clip processing of the control signalcombining circuitry is independently programmably configurable.
 29. Thedigital filter of claim 9, wherein: at least some of the plurality ofcomponent control signal generation circuitry are programmablyconfigurable.
 30. The digital filter of claim 9, wherein: the controlsignal combining circuitry is programmably configurable.
 31. The digitalfilter of claim 1, wherein: at least some of the plurality of componentcontrol signal generation circuitry are programmably configurable; andthe control signal combining circuitry is programmably configurable. 32.The digital filter of claim 1, wherein: the component digital filtersare connected serially.
 33. The digital filter of claim 2, wherein:processing the received tap output signals by the control signalgeneration circuitry is programmably configurable on a sample by samplebasis.
 34. The digital filter of claim 1, wherein: the component digitalfilters are connected in a combination of serially and in parallel. 35.The digital filter of claim 2, wherein: processing the received tapoutput signals by the control signal generation circuitry isprogrammably configurable on a sample by sample basis of an input signalto the digital filter.
 36. A method of configuring a digital filter,wherein the digital filter includes: a plurality of connected componentdigital filters; control signal generation circuitry configured to:receive a tap output signal from each of at least some of the componentdigital filters; and process the received tap output signals to generatea control signal to output from the control signal circuitry; and outputprocessing circuitry configured to process an output of one of thecomponent digital filters, based on the control signal generated by thecontrol signal circuitry, to generate an output of the digital filter,the method comprising: programmably configuring the processing of thereceived tap output signals by the control signal generation circuitryto achieve desired output characteristics of the digital filter whilerefraining from modifying the operation of the component digital filtersand from reconfiguring the provision of tap output signals, whereby thedigital filter is adaptable for use in different applications.